EP2AGX95EF29C6N Datasheet, PDF (212/380 Pages) Altera Corporation – Device Interfaces and Integration

7–10
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7–7 shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX45
and EP2AGX65 devices in the 780-pin FineLine BGA package.
Figure 7–7. Number of DQ/DQS Groups per Bank in EP2AGX45 and EP2AGX65 Devices in the 780-Pin FineLine BGA
Package (Note 1)
I/O Bank 8A
54 User I/Os
×4=6
×8/×9=3
×16/×18=1
×32/×36=0
I/O Bank 7A
70 User I/Os
×4=8
×8/×9=4
×16/×18=2
×32/×36=1
EP2AGX45 and EP2AGX65
Devices in the 780-Pin FineLine BGA
I/O Bank 6A (2)
50 User I/Os
×4=6
×8/×9=3
×16/×18=1
×32/×36=0
I/O Bank 5A
66 User I/Os
×4=8
×8/×9=4
×16/×18=2
×32/×36=1
I/O Bank 3A
54 User I/Os
×4=6
×8/×9=3
×16/×18=1
×32/×36=0
I/O Bank 4A
70 User I/Os
×4=8
×8/×9=4
×16/×18=2
×32/×36=1
Notes to Figure 7–7:
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of their pin members used for
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation