EP2AGX95EF29C6N Datasheet, PDF (172/380 Pages) Altera Corporation – Device Interfaces and Integration

Table 6–4. Available I/O Pins in Each Arria II GZ I/O Bank (Note 1)
Package
Device
Bank
Total
1A 1C 2A 2C 3A 3B 3C 4A 4B 4C 5A 5C 6A 6C 7A 7B 7C 8A 8B 8C
780-pin
Flip Chip
FBGA
EP2AGZ300 — 1 — — 40 — 28 40 — 30 — — — — 40 — 30 40 — 32 281
EP2AGZ350 — 1 — — 40 — 28 40 — 30 — — — — 40 — 30 40 — 32 281
1152-pin
Flip Chip
FBGA
EP2AGZ225 46 42 — — 40 24 30 40 24 30 — — 46 42 40 24 30 40 24 32 554
EP2AGZ300 46 42 — — 40 24 30 40 24 30 — — 46 42 40 24 30 40 24 32 554
EP2AGZ350 46 42 — — 40 24 30 40 24 30 — — 46 42 40 24 30 40 24 32 554
1517-pin
Flip Chip
FBGA
EP2AGZ225 46 42 48 42 40 24 30 40 24 30 48 42 46 42 40 24 30 40 24 32 734
EP2AGZ300 46 42 48 42 40 24 30 40 24 30 48 42 46 42 40 24 30 40 24 32 734
EP2AGZ350 46 42 48 42 40 24 30 40 24 30 48 42 46 42 40 24 30 40 24 32 734
Note to Table 6–4:
(1) The number of I/O pins include all general purpose I/Os, dedicated clock pins, and dual-purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in the I/O pin
count.