EP2AGX95EF29C6N Datasheet, PDF (238/380 Pages) Altera Corporation – Device Interfaces and Integration

7–36
Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
In addition to the dedicated postamble register, Arria II GZ devices also have a
half-data rate (HDR) block inside the postamble enable circuitry. Use these registers if
the controller is running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit (shown in
Figure 7–26 on page 7–39).
There is an AND gate after the postamble register outputs that is used to avoid
postamble glitches from a previous read burst on a non-consecutive read burst. This
scheme allows a half-a-clock cycle latency for dqsenable assertion and zero latency for
dqsenable de-assertion shown in Figure 7–23.
Figure 7–23. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
Pos tam ble
Postamble glitch
Pream ble
DQS
Postamble Enable
dqsenable
Delayed by
1/2T logic
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation