EP2AGX95EF29C6N Datasheet, PDF (254/380 Pages) Altera Corporation – Device Interfaces and Integration

8–8
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Transmitter
Differential Transmitter
The Arria II transmitter has a dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and
PLLs that can be shared between the transmitter and receiver. The differential buffer
can drive out LVDS, mini-LVDS, and RSDS signaling levels. The differential output
buffer supports programmable pre-emphasis and programmable voltage output
differential (V_OD) controls, and can drive out mini-LVDS and RSDS signaling levels.
Figure 8–4 is a block diagram of the LVDS transmitter.
1 When using emulated LVDS I/O standards at the differential transmitter, the SERDES
circuitry must be implemented in logic cells but not hard SERDES.
Figure 8–4. LVDS Transmitter Block Diagram (Note 1), (2)
tx_in ¹⁰
Serializer 2
IOE
DIN DOUT
IOE supports SDR, DDR, or
Non-Registered Datapath
tx_out
+
-
FPGA
Fabric
tx_coreclock
LVDS Transmitter
3 _{(LVDS_LOAD_EN, diffioclk, tx_coreclock)}
PLL (3)
tx_inclock
Notes to Figure 8–4:
(1) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(2) The tx_in port has a maximum data width of 10 bits.
(3) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
LVDS Clock Domain
Serializer
The serializer takes parallel data from the FPGA fabric, clocks it into the parallel load
registers, and serializes it using the shift registers before sending the data to the
differential output buffer. The MSB of the parallel data is transmitted first. The
parallel load and shift registers are clocked by the high-speed clock running at the
serial data rate (diffioclk) and controlled by the load enable signal (LVDS_LOAD_EN)
generated from the PLL. You can statically set the serialization factor to x4, x6, x7, x8,
or x10 using the ALTLVDS megafunction. The load enable signal is derived from the
serialization factor setting.
You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve
a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data
output registers that can each operate in either DDR or SDR mode. Figure 8–5 shows
the serializer bypass path.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation