EP2AGX95EF29C6N Datasheet, PDF (225/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
7–23
Table 7–4 lists the possible combinations to use two ×16/×18 DQ/DQS groups to form
a ×32/×36 group on Arria II devices lacking a native ×32/×36 DQ/DQS group.
Table 7–4. Possible Group Combinations in Arria II Devices
Device
Package
Device Density
I/O Bank Combinations
358-Pin Ultra FineLine BGA
■ EP2AGX45
■ EP2AGX65
4A and 7A (Top and Bottom I/O banks) (1)
572-Pin FineLine BGA
■ EP2AGX45
■ EP2AGX65
■ EP2AGX95
■ EP2AGX125
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
Arria II GX
780-Pin FineLine BGA (2)
■ EP2AGX45
■ EP2AGX65
■ EP2AGX95
■ EP2AGX125
■ EP2AGX190
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
■ EP2AGX260
1152-Pin FineLine BGA (2)
■ EP2AGX95
■ EP2AGX125
■ EP2AGX190
■ EP2AGX260
7A and 8A (Top I/O banks)
5A and 6A (Right I/O banks)
3A and 4A (Bottom I/O banks)
Combine any two banks from each side of I/O banks
780-Pin FineLine BGA
■ EP2AGZ300
■ EP2AGZ350
3A and 4A, 7A and 8A (bottom and top I/O banks) (3)
1152-Pin FineLine BGA
Arria II GZ
■ EP2AGZ225
■ EP2AGZ300 (4)
■ EP2AGZ350 (4)
1A and 1C, 6A and 6C (left and right I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1517-Pin FineLine BGA
■ EP2AGZ225
■ EP2AGZ300 (4)
■ EP2AGZ350 (4)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
Notes to Table 7–4:
(1) Only one ×8/×9 group left in each of the remaining I/O banks. You can form only 36 group write data with four 8/9 groups in these packages.
(2) This device supports 36 DQ/DQS groups on each side of I/O banks.
(3) Each side of the device in these packages has four remaining ×8/×9 groups. You can combine them for the write side (only) if you want to keep
the ×36 QDR II+/QDR II SRAM interface on one side of the device. In this case, you must change the Memory Interface Data Group default
assignment from the default 18 to 9.
(4) This device supports ×36 DQ/DQS groups on the top and bottom I/O banks natively.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration