EP2AGX95EF29C6N Datasheet, PDF (275/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
8–29
Using Both Center PLLs
You can use center PLLs to drive DPA-enabled channels simultaneously, if they drive
these channels in their adjacent banks only, as shown in Figure 8–23.
1 Center PLLs are available at the right I/O banks of Arria II GX devices and the right
and left I/O banks of Arria II GZ devices.
If one of the center PLLs drives the DPA-enabled channels in the upper and lower I/O
banks, you cannot use the other center PLL for DPA-enabled channels, as shown in
Figure 8–24.
Figure 8–24. Center PLLs Driving DPA-Enabled Differential I/Os
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
PLL
Center
PLL
Center
PLL
Center
PLL
Unused
PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration