EP2AGX95EF29C6N Datasheet, PDF (216/380 Pages) Altera Corporation – Device Interfaces and Integration

7–14
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7–11 shows the number of DQ/DQS groups per bank in Arria II GZ
EP2AGZ300 and EP2AGZ350 devices in the 780-pin FineLine BGA package.
Figure 7–11. Number of DQ/DQS Groups per Bank in EP2AGZ300 and EP2AGZ350 Devices in the 780-Pin FineLine BGA
Package, (Note 1)
DLL0
I/O Bank 8A
40 User I/Os
×4=6
×8/×9=3
×16/×18=1
I/O Bank 8C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 7C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 7A
40 User I/Os
×4=6
×8/×9=3
×16/×18=1
DLL3
EP2AGZ300 and EP2AGZ350 Devices
in the 780-Pin FineLine BGA
DLL1
I/O Bank 3A
40 User I/Os
×4=6
×8/×9=3
×16/×18=1
I/O Bank 3C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 4C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 4A
40 User I/Os
×4=6
×8/×9=3
×16/×18=1
DLL2
Note to Figure 7–11:
(1) EP2AGZ300 and EP2AGZ350 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface” on page 7–21.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation