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EP2AGX95EF29C6N Datasheet, PDF (161/380 Pages) Altera Corporation – Device Interfaces and Integration
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–53
PHASEUPDOWN and PHASECOUNTERSELECT signals are synchronous to SCANCLK and must
meet the tsu and th requirements with respect to the SCANCLK edges.
1 You can repeat dynamic phase-shifting indefinitely. For example, in a design where
the VCO frequency is set to 1,000 MHz and the output clock frequency is set to
100 MHz, performing 40 dynamic phase shifts (each one yields 125 ps phase shift)
results in shifting the output clock by 180°, in other words, a phase shift of 5 ns.
The PHASESTEP signal is latched on the negative edge of SCANCLK (a,c) and must remain
asserted for at least two SCANCLK cycles. De-assert PHASESTEP after PHASEDONE goes
low. On the second SCANCLK rising edge (b,d) after PHASESTEP is latched, the values of
PHASEUPDOWN and PHASECOUNTERSELECT are latched and the PLL starts dynamic
phase-shifting for the specified counters and in the indicated direction. PHASEDONE is
de-asserted synchronous to SCANCLK at the second rising edge (b,d) and remains low
until the PLL finishes dynamic phase-shifting. Depending on the VCO and SCANCLK
frequencies, PHASEDONE low time may be greater than or less than one SCANCLK cycle.
You can perform another dynamic phase-shift after the PHASEDONE signal goes from
low to high. Each PHASESTEP pulse enables one phase shift. PHASESTEP pulses must be
at least one SCANCLK cycle apart.
Figure 5–44 shows the dynamic phase shifting waveform.
Figure 5–44. Dynamic Phase Shifting Waveform for Arria II Devices
SCANCLK
PHASESTEP
PHASEUPDOWN
PHASECOUNTERSELECT
PHASEDONE
a
b
c
d
PHASEDONE goes low synchronous with SCANCLK
t CONFIGPHASE
f For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager
interface, refer to the Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG)
Megafunction User Guide.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration