EP2AGX95EF29C6N Datasheet, PDF (17/380 Pages) Altera Corporation – Device Interfaces and Integration

Table 1–1 lists the Arria II device features.
Table 1–1. Features in Arria II Devices
Feature
EP2AGX45 EP2AGX65
Arria II GX Devices
Arria II GZ Devices
EP2AGX95 EP2AGX125 EP2AGX190 EP2AGX260 EP2AGZ225 EP2AGZ300 EP2AGZ350
Total Transceivers (1)
8
8
12
ALMs
18,050
25,300
37,470
LEs
42,959
60,214
89,178
PCIe hard IP blocks
1
1
1
M9K Blocks
319
495
612
M144K Blocks
—
—
—
Total Embedded Memory in M9K
Blocks (Kbits)
2,871
4,455
5,508
Total On-Chip Memory
(M9K +M144K + MLABs) (Kbits)
3,435
5,246
6,679
Embedded Multipliers (18 x 18) (2) 232
312
448
General Purpose PLLs
4
4
6
Transceiver TX PLLs (3), (4)
2 or 4
2 or 4
4 or 6
User I/O Banks (5), (6)
6
6
8
High-Speed LVDS SERDES
(up to 1.25 Gbps) (7)
8, 24, or 28 8, 24, or 28 24, 28, or 32
12
49,640
118,143
1
730
—
6,570
8,121
576
6
4 or 6
8
24, 28, 32
16
76,120
181,165
1
840
—
7,560
9,939
656
6
6 or 8
12
28 or 48
16
102,600
244,188
1
950
—
8,550
11,756
736
6
6 or 8
12
24 or 48
16 or 24
89,600
224,000
1
1,235
—
11,115
16 or 24
119,200
298,000
1
1,248
24
14,688
16 or 24
139,400
348,500
1
1,248
36
16,416
13,915
800
6 or 8
8 or 12
16 or 20
42 or 86
18,413
20,772
920
4, 6, or 8
8 or 12
8, 16, or 20
1,040
4, 6, or 8
8 or 12
8, 16, or 20
0 (8), 42, or 86 0 (8), 42, or 86
Notes to Table 1–1:
(1) The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only on
the right side of the device.
(2) This is in four multiplier adder mode.
(3) The FPGA fabric can use these phase locked-loops (PLLs) if they are not used by the transceiver.
(4) The number of PLLs depends on the package. Transceiver transmitter (TX) PLL count = (number of transceiver blocks) × 2.
(5) Banks 3C and 8C are dedicated configuration banks and do not have user I/O pins.
(6) For Arria II GZ devices, the user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins
are not included in the pin count.
(7) For Arria II GZ devices, total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX. For more information, refer to the High-Speed I/O Interfaces and DPA in Arria II Devices chapter.
(8) The smallest pin package (780-pin package) does not support high-speed LVDS SERDES.