EP2AGX95EF29C6N Datasheet, PDF (249/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
8–3
Locations of the I/O Banks
Locations of the I/O Banks
Arria II I/Os are divided into 16 to 20 I/O banks. For Arria II GX devices, the
high-speed differential I/O s are located at the right side of the device. For Arria II GZ
devices, the high-speed differential I/Os are located at the right and left sides of the
device.
Figure 8–1 and Figure 8–2 show a high-level chip overview of Arria II devices.
Figure 8–1. High-Speed Differential I/Os with DPA Block Locations in an Arria II GX Device (Note 1), (2), (3)
High-Speed Differential I/O,
General Purpose I/O,
and Memory Interface
High-Speed Differential I/O,
General Purpose I/O,
and Memory Interface
PLL
PLL
High-Speed
Differential
I/O with DPA,
General
Purpose
I/O, and
Memory
Interface
Transceiver
FPGA Fabric
PLL
Blocks
(Logic Elements, DSP,
Embedded Memory, and Clock Networks)
PLL
High-Speed
Differential
I/O with DPA,
General
Purpose
I/O, and
Memory
Interface
PLL
PLL
High-Speed Differential I/O,
General Purpose I/O,
and Memory Interface
High-Speed Differential I/O,
General Purpose I/O,
and Memory Interface
Notes to Figure 8–1:
(1) This figure is a top view of the silicon die, which corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(2) Applicable to EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(3) There are no center PLLs on the right I/O banks for EP2AGX45 and EP2AGX65 devices.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration