EP2AGX95EF29C6N Datasheet, PDF (112/380 Pages) Altera Corporation – Device Interfaces and Integration

5–4
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–2. GCLK Networks in Arria II GZ Devices
C LK[12..15]
T1 T2
GCLK[12..15]
CLK[0..3] ^{L2 GCLK[0..3]}
L3
GCLK[8..11] _{R2 CLK[8..11]}
R3
GCLK[4..7]
B1 B2
CLK[4..7]
Regional Clock Networks
For Arria II devices, the RCLK networks only pertain to the quadrant they drive into.
RCLK networks provide the lowest clock delay and skew for logic contained in a
single device quadrant. Arria II IOEs and internal logic in a given quadrant can also
drive RCLKs to create internally generated RCLKs and other high fan-out control
signals; for example, synchronous or asynchronous clears and clock enables.
Figure 5–3 and Figure 5–4 show CLK pins and PLLs that can drive RCLK networks in
Arria II devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation