EP2AGX95EF29C6N Datasheet, PDF (201/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
Document Revision History
6–37
I/O Placement Guidelines
This section provides I/O placement guidelines for the programmable I/O standards
supported by Arria II devices and includes essential information for designing
systems with an Arria II device’s selectable I/O capabilities.
3.3-V, 3.0-V, and 2.5-V LVTTL/LVCMOS Tolerance Guidelines
Altera recommends the following techniques when you use 3.3-, 3.0-, and 2.5-V I/O
standards to limit overshoot and undershoot at I/O pins:
■ Low drive strength or series termination—the impedance of the I/O driver must
be equal to or greater than the board trace impedance to minimize overshoot and
undershoot at the un-terminated receiver end. If high driver strength (lower driver
impedance) is required, Altera recommends series termination at the driver end
(on-chip or off-chip).
■ Output slew rate—Arria II GX devices have two levels and Arria II GZ devices
have four levels of slew rate control for single-ended output buffers. Slow slew
rate can significantly reduce the overshoot and undershoot in the system at the
cost of slightly slower performance.
■ Input clamping diodes—Arria II I/Os have on-chip clamping diodes. These
clamping diodes are required for PCI/PCI-X standards and recommended for
3.3-V LVTTL/CMOS standards.
■ When you use clamping diodes, the floating well of the I/O is clamped to V_CCIO.
As a result, the Arria II device might draw extra input leakage current from the
external input driver. This may violate the hot-socket DC- and AC-current
specification and increase power consumption. With the clamping diode enabled,
the Arria II device supports a maximum DC current of 8 mA.
Pin Placement Guideline
To validate your pin placement, Altera recommends creating a Quartus II design,
entering in your device I/O assignments, and compiling your design. The Quartus II
software checks your pin connections with respect to I/O assignment and placement
rules to ensure proper device operation. These rules are dependent on device density,
package, I/O assignments, voltage assignments, and other factors that are not
described in this chapter.
Document Revision History
Table 6–14 lists the revision history for this chapter.
Table 6–14. Document Revision History (Part 1 of 2)
Date
December 2011
June 2011
Version
Changes
■ Updated Table 6–2 and Table 6–11.
4.2
■ Minor text edits.
■ Updated Table 6–9 and Table 6–10.
4.1 ■ Updated Figure 6–3 and Figure 6–4.
■ Minor text edits.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration