EP2AGX95EF29C6N Datasheet, PDF (227/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
7–25
Figure 7–18 and Figure 7–19 show how the DQS phase-shift circuitry is connected to
the DQS/CQ and CQn pins in the device where memory interfaces are supported on
the top, bottom, and right sides of the Arria II GX device and all sides of the
Arria II GZ device.
Figure 7–18. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry for Arria II GX Devices (Note 1)
DLL
Reference
Clock (2)
DQS/CQ CQn
Pin
Pin
Δt
Δt
DQS/CQ
Pin
CQn
Pin
DQS Logic
Blocks
Δt
Δt
DQS
Phase-Shift
Circuitry
to IOE
6
6
to IOE
to IOE to IOE
to
IOE
DQS Logic
Blocks
Δt
CQn
Pin
to
Δt
DQS/CQ
IOE
Pin
to
IOE
Δt
CQn
Pin
to
IOE
Δt
DQS/CQ
Pin
6
6
to IOE to IOE
to IOE to IOE
DQS
Phase-Shift
Circuitry
Δt
Δt
Δt
Δt
CQn DQS/CQ
Pin
Pin
CQn DQS/CQ
Pin
Pin
DLL
Reference
Clock (2)
Notes to Figure 7–18:
(1) For possible reference input clock pins for each DLL, refer to “DLL” on page 7–27.
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration