EP2AGX95EF29C6N Datasheet, PDF (100/380 Pages) Altera Corporation – Device Interfaces and Integration

4–24
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
High-Precision Multiplier Adder Mode
In the high-precision multiplier adder, the DSP block can implement 2 two-multiplier
adders, with a multiplier precision of 18 × 36 (one two-multiplier adder per half-DSP
block). This mode is useful in filtering or FFT applications where a datapath greater
than 18 bits is required, yet 18 bits is sufficient for coefficient precision. This can occur
if data has a high dynamic range. If the coefficients are fixed, as in FFT and most filter
applications, the precision of 18 bits provides a dynamic range over 100 dB, if the
largest coefficient is normalized to the maximum 18-bit representation.
In these situations, the datapath can be up to 36 bits, allowing sufficient capacity for
bit growth or gain changes in the signal source without loss of precision, which is
useful in single precision block floating point applications. Figure 4–17 shows the
high-precision multiplier is performed in two stages. The sum of the results of the two
adders produce the final result:
Z[54..0] = P₀[53..0] + P₁[53..0]
where P₀ = A[17..0] × B[35..0] and P₁ = C[17..0] × D[35..0]
Figure 4–17. High-Precision Multiplier Adder Configuration for Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
overflow (1)
dataA[0:17]
dataB[0:17]
dataA[0:17]
dataB[18:35]
dataC[0:17]
+
P₀
<<18
+
result[ ]
dataD[0:17]
dataC[0:17]
+
P₁
dataD[18:35]
<<18
Half-DSP Block
Note to Figure 4–17:
(1) Block output for accumulator overflow and saturate overflow.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation