EP2AGX95EF29C6N Datasheet, PDF (32/380 Pages) Altera Corporation – Device Interfaces and Integration

2–2
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Logic Array Blocks
The LAB of the Arria II device has a derivative called memory LAB (MLAB), which
adds look-up table (LUT)-based SRAM capability to the LAB. The MLAB supports a
maximum of 640 bits of simple dual-port SRAM. You can configure each ALM in an
MLAB as either a 64 × 1 or 32 × 2 block, resulting in a configuration of 64 × 10 or
32 × 20 simple dual-port SRAM blocks. MLAB and LAB blocks always coexist as pairs
in Arria II devices. MLAB is a superset of the LAB and includes all LAB features.
Figure 2–2 shows an overview of LAB and MLAB topology.
f For more information about MLABs, refer to the TriMatrix Memory Blocks in Arria II
Devices chapter.
Figure 2–2. LAB and MLAB Structure in Arria II Devices
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
ALM
ALM
ALM
ALM
ALM
LAB Control Block LAB Control Block
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
ALM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
ALM
ALM
LUT-based-64 x 1 ⁽¹⁾
Simple dual port SRAM
LUT-based-64 x 1 (1)
Simple dual port SRAM
ALM
ALM
MLAB
LAB
Note to Figure 2–2:
(1) You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation