EP2AGX95EF29C6N Datasheet, PDF (144/380 Pages) Altera Corporation – Device Interfaces and Integration

5–36
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Programmable Duty Cycle
The programmable duty cycle allows the PLLs to generate clock outputs with a
variable duty cycle. This feature is supported on the PLL post-scale counters. The
duty-cycle setting is achieved by a low and high time-count setting for the post-scale
counters. The Quartus II software uses the frequency input and the required multiply
or divide rate to determine the duty cycle choices. The post-scale counter value
determines the precision of the duty cycle. The precision is defined by 50% divided by
the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are
possible for duty-cycle choices between 5% to 90%.
Combining the programmable duty cycle with programmable phase shift allows the
generation of precise non-overlapping clocks.
For Arria II GZ devices, if the PLL is in external feedback mode, set the duty cycle for
the counter driving the fbin pin to 50%.
Programmable Phase Shift
Use phase shift to implement a robust solution for clock delays in Arria II devices.
Implement phase shift with a combination of the VCO phase output and the counter
starting time. A combination of the VCO phase output and counter starting time is the
most accurate method of inserting delays because it is purely based on counter
settings, which are independent of process, voltage, and temperature (PVT).
You can phase-shift the output clocks from the Arria II PLLs in either of these two
resolutions:
■ Fine resolution with VCO phase taps
■ Coarse resolution with counter starting time
Fine-resolution phase shifts are implemented by allowing any of the output counters
(C[n..0]) or the m counter to use any of the eight phases of the VCO as the reference
clock. This allows you to adjust the delay time with a fine resolution. The minimum
delay time that you can insert with this method is defined in Equation 5–1.
Equation 5–1. Fine-Resolution Phase Shifts for Arria II Devices
Φ_fine =
1
8
T_VCO
=
1
8f_VCO
=
N
8Mf_REF
where f_REF is the input reference clock frequency.
For example, if f_REF is 100 MHz, n is 1, and m is 8, then f_VCO is 800 MHz and _fine
equals 156.25 ps. The PLL operating frequency, which is governed by the reference
clock frequency and the counter settings, defines this phase shift.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation