EP2AGX95EF29C6N Datasheet, PDF (301/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
9–15
FPP Configuration Timing
Figure 9–4 shows the timing waveform for an FPP configuration when using a
MAX II device as an external host. This waveform shows timing when the
decompression and design security features are not enabled.
Figure 9–4. FPP Configuration Timing Waveform with Decompression and Design Security not Enabled (Note 1), (2)
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
nSTATUS (3)
CONF_DONE (4)
DCLK
DATA[7..0]
User I/O
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Byte 0 Byte 1 Byte 2 Byte 3
t_DSU
High-Z
(5)
Byte n-2 Byte n-1 Byte n
(6)
(7)
User Mode
User Mode
INIT_DONE
t_CD2UM
Notes to Figure 9–4:
(1) Use this timing waveform when you do not use the decompression and design security features.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(3) After power-up, the Arria II device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device.
(6) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(7) DATA[7..1] are available as user I/O pins after configuration. The state of these pins depends on the dual-purpose pin settings. For Arria II GX
devices, DATA[0] is a dedicated pin that is used for both the PS and AS configuration modes and is not available as a user I/O pin after
configuration. For Arria II GZ devices, DATA[0] is available as a user I/O pin after configuration.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration