EP2AGX95EF29C6N Datasheet, PDF (133/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–25
Figure 5–22 shows the clock I/O pins associated with the top and bottom PLLs.
Figure 5–22. External Clock Outputs for Top and Bottom PLLs in Arria II GZ Devices
Notes to Figure 5–22:
(1) You can feed these clock output pins using any one of the C[9..0], or m counters.
(2) The CLKOUT0p and CLKOUT0n pins can be either single-ended or differential clock outputs. The CLKOUT1 and CLKOUT2 pins are
dual-purpose I/O pins that you can use as two single-ended outputs or one differential external feedback input pin. The CLKOUT3 and CLKOUT4
pins are two single-ended output pins.
(3) These external clock enable signals are available only when you use the ALTCLKCTRL megafunction.
For Arria II GZ devices, any of the output counters (C[9..0] on the top and bottom
PLLs and C[6..0] on the left and right PLLs) or the M counter can feed the dedicated
external clock outputs, as shown in Figure 5–22 and Figure 5–23. Therefore, one
counter or frequency can drive all the output pins available from a given PLL. Each
left and right PLL supports two clock I/O pins, configured as either two single-ended
I/Os or one differential I/O pair. When using both pins as single-ended I/Os, one of
them can be the clock output while the other pin is the external feedback input (FB)
pin. Therefore, for single-ended I/O standards, the left and right PLLs only support
external feedback mode.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration