EP2AGX95EF29C6N Datasheet, PDF (211/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
7–9
Memory Interfaces Pin Support for Arria II Devices
Figure 7–6 shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX95
and EP2AGX125 devices in the 572-pin FineLine BGA package.
Figure 7–6. Number of DQ/DQS Groups per Bank in EP2AGX95 and EP2AGX125 Devices in the 572-Pin FineLine BGA
Package (Note 1), (2)
I/O Bank 8A
42 User I/Os
×4=4
×8/×9=2
×16/×18=1
×32/×36=0
I/O Bank 7A
38 User I/Os
×4=4
×8/×9=2
×16/×18=1
×32/×36=0
EP2AGX95 and EP2AGX125
Devices in the 572-Pin FineLine BGA
I/O Bank 3A
38 User I/Os
×4=4
×8/×9=2
×16/×18=1
×32/×36=0
I/O Bank 4A
42 User I/Os
×4=4
×8/×9=2
×16/×18=1
×32/×36=0
I/O Bank 6A (3)
50 User I/Os
×4=6
×8/×9=3
×16/×18=1
×32/×36=0
I/O Bank 5A
50 User I/Os
×4=6
×8/×9=3
×16/×18=1
×32/×36=0
Notes to Figure 7–6:
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Arria II GX devices in the 572-pin FineLine BGA Package do not support the 36 QDR II+/QDR II SRAM interface.
(3) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of their pin members used for
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration