EP2AGX95EF29C6N Datasheet, PDF (298/380 Pages) Altera Corporation – Device Interfaces and Integration

9–12
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
1 If you use the Arria II decompression and/or design security features, the external
host must send a DCLK frequency that is x4 the data rate.
The x4 DCLK signal does not require an additional pin and is sent on the DCLK pin. The
maximum DCLK frequency is 125 MHz, which results in a maximum data rate of
250 Mbps. For Arria II GX devices, if you are not using the decompression or design
security features, the data rate is x1 the DCLK frequency. For Arria II GZ devices, if you
are not using the decompression or design security features, the data rate is x8 the
DCLK frequency.
Figure 9–1 shows the configuration interface connections between an Arria II device
and a MAX II device for single device configuration.
Figure 9–1. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
External Host
(MAX II Device or
Microprocessor)
(1) (1)
(2)
10 kΩ
10 kΩ 10 kΩ
GND
Arria II Device
MSEL[n..0]
CONF_DONE
nSTATUS
nCE
nCEO
(4)
N.C. (3)
DATA[7..0]
nCONFIG
DCLK
Notes to Figure 9–1:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V_CCIO pin.
For Arria II GZ devices, use the V_CCPGM pin. V_CCIO/V_CCPGM must be high enough to meet the V_IH specification of the I/O on both the device and the
external host. Altera recommends powering up the configuration system I/Os with V_CCIO/V_CCPGM.
(2) A pull-up resistor to V_CCIO/V_CCPGM or a pull-down resistor keeps the nCONFIG line in a known state when the external host is not driving the line.
(3) You can leave the nCEO pin unconnected or used as a user I/O pin when it does not feed the nCE pin of the other device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to Table 9–7 on page 9–10.
1 Arria II devices receive configuration data on the DATA[7..0] pins and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK. If
you are using the Arria II decompression, design security, or both features,
configuration data is latched on the rising edge of every first DCLK cycle out of the four
DCLK cycles. Altera recommends keeping the data on DATA[7..0] stable for the next
three clock cycles while the data is being processed. You can only stop DCLK three
clock cycles after the last data is latched.
In Arria II devices, the initialization clock source is either the internal oscillator or the
optional CLKUSR pin. By default, the internal oscillator is the clock source for
initialization. If you use the internal oscillator, the Arria II device provides itself with
enough clock cycles for proper initialization. Therefore, if the internal oscillator is the
initialization clock source, sending the entire configuration file to the device is
sufficient to configure and initialize the device. Driving DCLK to the device after
configuration is complete does not affect device operation.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation