EP2AGX95EF29C6N Datasheet, PDF (135/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–27
PLL Control Signals
You can use the pfdena, areset, and locked signals to observe and control PLL
operation and resynchronization.
pfdena
Use the pfdena signal to maintain the most recent locked frequency to allow your
system to store its current settings before shutting down. The pfdena signal controls
the phase frequency detector (PFD) output with a programmable gate. If you disable
the PFD, the VCO operates at its most recent set value of control voltage and
frequency with some long-term drift to a lower frequency.
areset
The areset signal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When areset is driven high,
the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The
VCO is then set back to its nominal setting. When areset is driven low again, the PLL
resynchronizes to its input as it relocks.
You must include the areset signal in designs if any of the following conditions are
true:
■ PLL reconfiguration or clock switchover is enabled in your design.
■ Phase relationships between the PLL input and output clocks must be maintained
after a loss-of-lock condition.
1 If the input clock to the PLL is not toggling or is unstable after power up, assert the
areset signal after the input clock is stable and in specifications.
locked
The locked signal indicates that the PLL has locked onto the reference clock and the
PLL clock outputs are operating at the desired phase and frequency set in the
Quartus II software.
1 Altera recommends using the areset and locked signals in your designs to control
and observe the status of your PLL.
f For more information about the PLL control signals, refer to the ALTPLL Megafunction
User Guide.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration