EP2AGX95EF29C6N Datasheet, PDF (49/380 Pages) Altera Corporation – Device Interfaces and Integration

December 2011
AIIGX51003-3.2
AIIGX51003-3.2
3. Memory Blocks in Arria II Devices
This chapter describes the Arria^® II device memory blocks that include 640-bit
memory logic array blocks (MLABs), 9-Kbit M9K blocks, and 144-Kbit M144K blocks.
MLABs are optimized to implement filter delay lines, small FIFO buffers, and shift
registers. You can use the M9K blocks for general purpose memory applications and
the M144K blocks for processor code storage, packet buffering, and video frame
buffering.
1 M144K block is only available for Arria II GZ devices.
You can configure each embedded memory block independently with the Quartus^® II
MegaWizard^™ Plug-In Manager to be a single- or dual-port RAM, FIFO, ROM, or shift
register. You can stitch together multiple blocks of the same type to produce larger
memories with a minimal timing penalty.
This chapter contains the following sections:
■ “Memory Features” on page 3–2
■ “Memory Modes” on page 3–10
■ “Clocking Modes” on page 3–19
■ “Design Considerations” on page 3–20
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011
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