EP2AGX95EF29C6N Datasheet, PDF (222/380 Pages) Altera Corporation – Device Interfaces and Integration

7–20
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
The numbering scheme starts from the top-left corner of the device going
counter-clockwise in a die top view. Figure 7–17 shows how the DQ/DQS groups are
numbered in a die top view of the device.
Figure 7–17. DQS Pins in Arria II GZ I/O Banks
DQS38T
DQS20T
DQS19T
DQS1T
DLL0
DLL3
PLL_L1
8A
8B
8C
DQS1L
1A
7C
7B
7A
PLL_R1
DQS34R
6A
1B
6B
1C
DQS17L
PLL_L2
PLL_L3
DQS18L
2C
Arria II GZ Device
6C
DQS18R
PLL_R2
PLL_R3
DQS17R
5C
2B
5B
2A
DQS34L
PLL_L4
3A
3B
3C
DLL1
DQS1B
DQS19B
5A
DQS1R
4C
4B
4A
PLL_R4
DQS20B
DLL2
DQS38B
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation