EP2AGX95EF29C6N Datasheet, PDF (262/380 Pages) Altera Corporation – Device Interfaces and Integration

8–16
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
Receiver Datapath Modes
Arria II devices support the following three receiver datapath modes:
■ “Non-DPA”
■ “DPA Mode”
■ “Soft CDR Mode”
Non-DPA
Non-DPA mode allows you to statically select the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for any
skew between the two signals. The reference clock must be a differential signal.
Figure 8–13 shows the non-DPA datapath block diagram. Input serial data is
registered at the rising or falling edge of the LVDS_diffioclk clock produced by the
PLL. You can select the rising/falling edge option using the ALTLVDS megafunction.
Both data realignment and deserializer blocks are clocked by the LVDS_diffioclk
clock.
For Arria II GX devices, you must perform PCB trace compensation to adjust the trace
length of each LVDS channel to improve channel-to-channel skew when interfacing
with non-DPA receivers at data rate above 840 Mbps.
The Quartus II software Fitter Report panel reports the amount of delay you must add
to each trace for the Arria II GX device. You can use the recommended trace delay
numbers published under the LVDS Transmitter/Receiver Package Skew
Compensation panel and manually compensate the skew on the PCB board trace to
reduce channel-to-channel skew, thus meeting the timing budget between LVDS
channels.
1 For more information about the LVDS Transmitter/Receiver Package Skew
Compensation report panel, refer to the “Arria II GX LVDS Package Skew
Compensation Report Panel“ section in the SERDES Transmitter/Receiver (ALTLVDS)
Megafunction User Guide.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation