EP2AGX95EF29C6N Datasheet, PDF (166/380 Pages) Altera Corporation – Device Interfaces and Integration

6–2
Chapter 6: I/O Features in Arria II Devices
I/O Standards Support
I/O Standards Support
Table 6–1 lists the supported I/O standards for Arria II GX devices and the typical
values for input and output V_CCIO, V_CCPD, V_REF, and board V_TT.
Table 6–1. I/O Standards and Voltage Levels for Arria II GX Devices
I/O Standard
Standard
Support
V_CCIO (V)
Input
Output
Operation Operation
V_CCPD (V)
V_REF (V)
3.3-V LVTTL/3.3-V LVCMOS
JESD8-B
3.3/3.0/2.5
3.3
3.0-V LVTTL/3.0-V LVCMOS
JESD8-B
3.3/3.0/2.5
3.0
2.5-V LVTTL/LVCMOS
JESD8-5
3.3/3.0/2.5
2.5
1.8-V LVTTL/LVCMOS
JESD8-7
1.8/1.5
1.8
1.5-V LVCMOS
JESD8-11
1.8/1.5
1.5
1.2-V LVCMOS
JESD8-12
1.2
1.2
3.0-V PCI
PCI Rev 2.2
3.0
3.0
3.0-V PCI-X (1)
PCI-X Rev 1.0
3.0
3.0
SSTL-2 Class I, II
JESD8-9B
(2)
2.5
SSTL-18 Class I, II
JESD8-15
(2)
1.8
SSTL-15 Class I
—
(2)
1.5
HSTL-18 Class I, II
JESD8-6
(2)
1.8
HSTL-15 Class I, II
JESD8-6
(2)
1.5
HSTL-12 Class I, II
JESD8-16A
(2)
1.2
Differential SSTL-2
JESD8-9B
(2), (3)
2.5
Differential SSTL-18
JESD8-15
(2), (3)
1.8
Differential SSTL-15
—
(2), (3)
1.5
Differential HSTL-18
JESD8-6
(2), (3)
1.8
Differential HSTL-15
JESD8-6
(2), (3)
1.5
Differential HSTL-12
JESD8-16A
(2), (3)
1.2
LVDS
ANSI/TIA/
EIA-644
(2)
2.5
RSDS and mini-LVDS
—
—
2.5
LVPECL
—
(2)
—
BLVDS
—
(2)
2.5
3.3
—
3.0
—
2.5
—
2.5
—
2.5
—
2.5
—
3.0
—
3.0
—
2.5
1.25
2.5
0.90
2.5
0.75
2.5
0.90
2.5
0.75
2.5
0.6
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
2.5
—
Notes to Table 6–1:
(1) PCI-X does not meet the PCI-X I-V curve requirement at the linear region.
(2) Single-ended SSTL/HSTL, differential SSTL/HSTL, LVDS, LVPECL, and BLVDS input buffers are powered by V_CCPD.
(3) Differential SSTL/HSTL inputs use LVDS differential input buffers without R_D OCT support.
V_TT (V)
—
—
—
—
—
—
—
—
1.25
0.90
0.75
0.90
0.75
0.6
1.25
0.90
0.75
0.90
0.75
0.60
—
—
—
—
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation