EP2AGX95EF29C6N Datasheet, PDF (208/380 Pages) Altera Corporation – Device Interfaces and Integration

7–6
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Table 7–2 lists the number of I/O modules and DQ/DQS groups per side of the
Arria II GX device. For a more detailed listing of the number of DQ/DQS groups
available per bank in each Arria II GX device, refer to Figure 7–4 on page 7–7 through
Figure 7–10 on page 7–13. These figures represent the die top view of the Arria II GX
device.
f For more information about DQ/DQS groups pin-out restriction format, refer to the
Arria II Device Family Pin Connection Guidelines.
Table 7–2. Number of DQ/DQS Groups and I/O Modules per Side in Arria II GX Devices
Device
Package
Side
Number of I/O
Module (1)
Number of DQ/DQS Groups
×4
×8/×9 ×16/×18 ×32/×36
Refer to
EP2AGX45 358-Pin Ultra ^Top/Bottom
3
EP2AGX65 FineLine BGA
Right
2
6
3
1
0 _{Figure 7–4 on}
4
2
0
0 ^{page 7–7}
EP2AGX45
EP2AGX65
572-Pin
Top/Bottom
4
EP2AGX95 ^{FineLine BGA}
EP2AGX125
Right
6
8
4
2
0
Figure 7–5 on
page 7–8
12
6
2
0
Figure 7–6 on
page 7–9
EP2AGX45
EP2AGX65
EP2AGX95 ^780-Pin
Top/Bottom/
EP2AGX125 ^{FineLine BGA}
Right
7
EP2AGX190
EP2AGX260
Figure 7–7 on
page 7–10
14
7
3
1
Figure 7–8 on
page 7–11
EP2AGX95 1152-Pin
Top/Bottom
9
EP2AGX125 FineLine BGA
Right
8
18
9
4
2 _{Figure 7–9 on}
16
8
4
2 ^{page 7–12}
EP2AGX190 1152-Pin
Top/Bottom/
EP2AGX260 FineLine BGA Right
12
24
12
6
2
Figure 7–10
on page 7–13
Note to Table 7–2:
(1) Each I/O module consists of 16 I/O pins. 12 of the 16 pins are DQ/DQS pins.
Table 7–3 lists the number of DQ/DQS groups available per side in each Arria II GZ
device. For a more detailed listing of the number of DQ/DQS groups available per
bank in each Arria II GZ device, refer to Figure 7–11 through Figure 7–15. These
figures represent the die top view of the Arria II GZ device.
Table 7–3. Number of DQ/DQS Groups per Side in Arria II GZ Devices (Part 1 of 2)
Device
EP2AGZ300
EP2AGZ350
EPAGZ225
EP2AGZ300
EP2AGZ350
Package
780-pin
FineLine BGA
1152-pin
FineLine BGA
1152-pin
FineLine BGA
Side
Left/Right
Top/Bottom
Left/Right
Top/Bottom
Left/Right
Top/Bottom
×4 (1)
0
18
13
26
13
26
Number of DQ/DQS Groups
×8/×9
0
8
6
12
6
12
×16/×18
0
2
2
4
2
4
×32/×36 (2)
0
0
0
0
0
2 (3)
Refer to
Figure 7–11 on
page 7–14
Figure 7–12 on
page 7–15
Figure 7–13 on
page 7–16
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation