EP2AGX95EF29C6N Datasheet, PDF (244/380 Pages) Altera Corporation – Device Interfaces and Integration

7–42
Chapter 7: External Memory Interfaces in Arria II Devices
Document Revision History
For Arria II GZ devices, the output path is designed to route combinatorial or
registered SDR outputs and full-rate or half-rate DDR outputs from the FPGA core.
Half-rate data is converted to full-rate using the HDR block, clocked by the half-rate
clock from the PLL.
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the ouput-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Document Revision History
Table 7–11 shows the revision history for this document.
Table 7–11. Document Revision History (Part 1 of 2)
Date
June 2011
December 2010
July 2010
November 2009
Version
Changes
■ Updated Table 7–3.
4.1 ■ Updated Figure 7–11, Figure 7–12, Figure 7–13, Figure 7–14, and Figure 7–15.
■ Minor text edits.
■ Updated for the Quartus II software version 10.1 release.
■ Added Arria II GZ devices information.
■ Added Figure 7–2, Figure 7–10, Figure 7–11, Figure 7–12, Figure 7–13, Figure 7–14,
Figure 7–15, Figure 7–17, Figure 7–19, Figure 7–24, Figure 7–26, and Figure 7–26.
4.0
■ Added Table 7–1, Table 7–3, Table 7–4, Table 7–5, Table 7–3, Table 7–4, Table 7–6,
Table 7–7, Table 7–8, and Table 7–9.
■ Updated Table 7–10.
■ Added “Using the RUP and RDN Pins in a DQ/DQS Group Used for Memory Interfaces in
Arria II GZ Devices” and “Arria II GZ Dynamic On-Chip Termination Control” sections.
■ Minor text edits.
Updated for Arria II GX v10.0 release:
■ Updated “Arria II Memory Interfaces Pin Support” section by adding reference to the
Section I. Device and Pin Planning in volume 2 of the External Memory Interface
3.0
Handbook and removing “Table 7–1: Memory Interface Pin Utilization”.
■ Update DLL numbering to match with the Quartus II software.
■ Minor text edits.
Updated for Arria II GX v9.1 release:
■ Updated Table 7–1, Table 7–2, and Table 7–5.
■ Updated Figure 7–1, Figure 7–2, Figure 7–3, Figure 7–11, Figure 7–12, Figure 7–13,
Figure 7–15, and Figure 7–16.
2.0
■ Updated the “Arria II GX External Memory Interface Features” section.
■ Added new “Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM
Interface” section.
■ Minor text edits.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation