EP2AGX95EF29C6N Datasheet, PDF (241/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
7–39
Figure 7–26 shows the registers available in the Arria II GZ input path. The input path
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
Figure 7–26. IOE Input Registers for Arria II GZ Devices (Note 1)
DQS/CQ (3), (9)
DQSn (9)
CQn (4)
DQ
Differential
Input
Buffer
Double Data Rate Input Registers
DQ
DFF
Input Reg AI
neg_reg_out
DQ
DQ
DFF
Input Reg BI
DFF
Input Reg CI
0
1
Alignment and Synchronization Registers
datain [0]
DQ
DFF
dataout
<bypass_output_register>(10)
Resynchronization Clock
(resync_clk_2×) (5)
datain [1]
(2)
DQ
DFF
dataout
Half Data Rate Registers
D
Q
DFF
directin
0
To Core
dataout[2] (7)
1
D
Q
DFF
DQ
DFF
D Q ^{To Core}
dataout [0] (7)
dataoutbypass
(8)
DFF
0
To Core
dataout [3] (7)
1
DQ
DFF
DQ
To Core
dataout [1] (7)
DFF
I/O Clock
Divider (6)
Half-Rate Resynchronization Clock (resync_clk_1×)
to core (7)
Notes to Figure 7–26:
(1) You can bypass each register block in this path.
(2) This is the 0-phase resynchronization clock.
(3) The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a GCLK line.
(4) This input clock comes from the CQn logic block.
(5) This resynchronization clock comes from a PLL through the clock network (resync_ck_2).
(6) The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL, the I/O clock divider can also be fed by the DQS bus or CQn
bus.
(7) The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
(8) You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data
rate register to feed dataout.
(9) The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS, and DQSn
signals are automatically inverted.
(10) The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/
synchronization register to feed dataout.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration