EP2AGX95EF29C6N Datasheet, PDF (84/380 Pages) Altera Corporation – Device Interfaces and Integration

4–8
Chapter 4: DSP Blocks in Arria II Devices
DSP Block Resource Descriptions
DSP Block Resource Descriptions
The DSP block consists of the following elements:
■ Input register bank
■ Four two-multiplier adders
■ Pipeline register bank
■ Second-stage adders
■ Four rounding and saturation logic units
■ Second adder register and output register bank
Figure 4–5 shows a detailed illustration of the overall architecture of the top half of the
DSP block. Table 4–9 on page 4–30 lists the DSP block dynamic signals.
Figure 4–5. Half-DSP Block Architecture
chainin[ ] (4)
scanina[ ]
clock[3..0]
ena[3..0]
alcr[3..0]
zero_loopback
accum_sload
zero_chainout
chainout_round
chainout_saturate
signa
signb
output_round
output_saturate
rotate
shift_right
overflow (1)
chainout_sat_overflow (2)
dataa_0[ ]
loopback
datab_0[ ]
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
(3)
result[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
Half-DSP Block
scanouta
chainout
Notes to Figure 4–5:
(1) Block output for accumulator overflow and saturate overflow.
(2) Block output for saturation overflow of chainout.
(3) When the chainout adder is not in use, the second adder register banks are known as output register banks.
(4) You must connect the chainin port to the chainout port of the previous DSP blocks; it must not be connected to general routings.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation