EP2AGX95EF29C6N Datasheet, PDF (176/380 Pages) Altera Corporation – Device Interfaces and Integration

6–12
Chapter 6: I/O Features in Arria II Devices
I/O Structure
Figure 6–4. IOE Structure for Arria II GZ Devices (Note 1), (2)
Firm Core
OE
from
Core
2
Half Data
Rate Block
OE Register
PRN
DQ
DQS Logic Block
D5_OCT
D6_OCT
Dynamic OCT Control (2)
Write
Data
from
Core
4
Half Data
Rate Block
clkout
To
Core
To
Core
D3_1
Delay
OE Register
PRN
DQ
Output Register
PRN
DQ
Output Register
PRN
DQ
D3_0
Delay
D5, D6
Delay
VCCIO
PCI Clamp
VCCIO
D5, D6
Delay
Programmable
Current
Strength and
Slew Rate
Control
Output Buffer
Programmable
Pull-Up Resistor
From OCT
Calibration
Block
On-Chip
Termination
D2 Delay
Open Drain
Input Buffer
D1
Delay
Input Register
PRN
DQ
Bus-Hold
Circuit
Read
Data
4
to
Core
Half Data
Rate Block
DQS
CQn
clkin
D4 Delay
Input Register
PRN
DQ
Input Register
PRN
DQ
Notes to Figure 6–4:
(1) The D3_0 and D3_1 delays have the same available settings in the Quartus^® II software.
(2) One dynamic OCT control is available per DQ/DQS group.
f For more information about I/O registers and how they are used for memory
applications, refer to the External Memory Interfaces in Arria II Devices chapter.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation