EP2AGX95EF29C6N Datasheet, PDF (64/380 Pages) Altera Corporation – Device Interfaces and Integration

3–16
Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Table 3–7 lists the possible M9K block mixed-port width configurations in true
dual-port mode.
Table 3–7. M9K Block Mixed-Width Configuration (True-Dual Port Mode)
Read Port
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
1K × 9
512 × 18
8K × 1
v
v
v
v
v
—
—
4K × 2
v
v
v
v
v
—
—
Write Port
2K × 4
v
v
v
v
v
—
—
1K × 8
v
v
v
v
v
—
—
512 × 16 1K × 9 512 × 18
v
—
—
v
—
—
v
—
—
v
—
—
v
—
—
—
v
v
—
v
v
Table 3–8 lists the possible M144K block mixed-port width configurations in true
dual-port mode.
Table 3–8. M144K Block Mixed-Width Configurations (True Dual-Port Mode)
Read Port
16K × 8
8K × 16
4K × 32
16K × 9
8K × 18
4K × 36
16K × 8
v
v
v
—
—
—
8K × 16
v
v
v
—
—
—
Write Port
4K × 32
v
v
v
—
—
—
16K × 9
—
—
—
v
v
v
8K × 18
—
—
—
v
v
v
4K × 36
—
—
—
v
v
v
In true dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output “new data” at that location or “old data”.
In true dual-port mode, you can access any memory location at any time from either
port. When accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens when you attempt to write to the
same address location from both ports at the same time. This results in unknown data
being stored to that address location. Conflict resolution circuitry is not built into the
Arria II memory blocks. You must handle address conflicts external to the RAM block.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation