EP2AGX95EF29C6N Datasheet, PDF (322/380 Pages) Altera Corporation – Device Interfaces and Integration

9–36
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
JTAG Configuration
Table 9–14. Dedicated Configuration Pin Connections During JTAG Configuration (Part 2 of 2)
Signal
nSTATUS
CONF_DONE
DCLK
Description
Pull to V_CCIO or V_CCPGM using a 10-k resistor. When configuring multiple devices in the same JTAG chain,
each nSTATUS pin must be pulled up to V_CCIO or V_CCPGM individually.
Pull to V_CCIO or V_CCPGM using a 10-k resistor. When configuring multiple devices in the same JTAG
chain, each CONF_DONE pin must be pulled up to V_CCIO or V_CCPGM individually. CONF_DONE going high at
the end of JTAG configuration indicates successful configuration.
Do not leave DCLK floating. Drive low or high, whichever is more convenient on your board.
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board
buffer.
JTAG-chain device programming is ideal when the system contains multiple devices
or when testing your system using JTAG BST circuitry.
Figure 9–17 shows a multi-device JTAG configuration when using a download cable.
Figure 9–17. JTAG Configuration of Multiple Devices Using a Download Cable
Download Cable
10-Pin Male Header
(JTAG Mode)
V_CCIO/V_CCPD
(2)
Pin 1
V_CCIO/
V_CCPD(2)
V_CCIO/
V_CCPD(2)
(3)
(3)
V_IO
(4)
Arria II Device
Arria II Device
StratiAx rIrIiaorIISDtreavtixceII GX
V_CCIO/V_CCPGM
(1)
V_CCIO/V_CCPGMV_CCIO/V_CCPGM
(1)
(1)
V_CCIO/V_CCPGM V_CCIO/V_CCPGM
(1)
(1)
Device
V_CCIO/V_CCPGM
(1)
10 kΩ
10 kΩ 10 kΩ
10 kΩ 10 kΩ
10 kΩ
nSTATUS
(5) _nCONFIG
CONF_DONE
(5) DCLK
(5) MSEL[n..0]
nCE (6)
nSTATUS
(5) _nCONFIG
CONF_DONE
(5)
DCLK
(5) MSEL[n..0]
nCE (6)
nSTATUS
(5)
nCONFIG
CONF_DONE
(5) DCLK
(5) MSEL[n..0]
nCE (6)
TDI
TDO
TMS TCK
TDI
TDO
TMS TCK
TDI
TDO
TMS TCK
1 kΩ
Notes to Figure 9–17:
(1) Connect the pull-up resistors to the V_CCIO power supply of I/O bank 3C for Arria II GX devices and to V_CCPGM (1.8-V, 2.5-V or 3.0-V) power supply
for Arria II GZ devices.
(2) You must connect the pull-up resistor to the same supply voltage, V_CCIO for Arria II GX devices or V_CCPD for Arria II GZ devices as the USB-Blaster,
ByteBlaster II, EthernetBlaster, or EthernetBlaster II cable.
(3) The resistor value can vary from 1 K to 10 K.
(4) In the USB-Blaster and ByteBlaster II cables, pin 6 is a no connect.
(5) You must connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use JTAG configuration, connect nCONFIG
to the V_CCIO for Arria II GX device, V_CCPGM for Arria II GZ device, and MSEL to GND. Pull DCLK either high or low, whichever is convenient on your
board.
(6) You must connect nCE to GND or drive it low for successful JTAG configuration.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation