EP2AGX95EF29C6N Datasheet, PDF (293/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
9–7
Configuration Process
Configuration Process
The following sections describe the general configuration process for FPP, standard
AS, fast AS, and PS schemes.
Power Up
To begin the configuration process, you must fully power the relevant voltage supply
to the appropriate voltage levels.
1 For an FPP configuration in Arria II GX devices, the DATA[7..1] pins are supplied by
V_CCIO for I/O bank 6A. You must power up this bank when you use the FPP
configuration. For Arria II GZ devices, the DATA[7..1] pins are powered up by
V_CCPGM during configuration or by V_CCIO if they are used as regular I/Os in user
mode.
Reset
After power up, the Arria II device goes through a POR. The POR delay depends on
the MSEL pin settings. During POR, the device resets, holds nSTATUS low, clears the
configuration RAM bits, and tri-states all user I/O pins. After the device successfully
exits POR, all user I/O pins continue to be tri-stated. While nCONFIG is low, the device
is in reset. When the device comes out of reset, nCONFIG must be at a logic-high level in
order for the device to release the open-drain nSTATUS pin. After nSTATUS is released, it
is pulled high by a pull-up resistor and the device is ready to receive configuration
data.
Before and during configuration, all user I/O pins are tri-stated. If nIO_pullup is
driven low during power up and configuration, the user I/O pins and dual-purpose
I/O pins have weak pull-up resistors, which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors are disabled.
Configuration
nCONFIG and nSTATUS must be at a logic-high level in order for the configuration stage
to begin. The device receives configuration data on its DATA pins and (for synchronous
configuration schemes) the clock source on the DCLK pin. Configuration data is latched
into the FPGA on the rising edge of DCLK. After the FPGA has received all the
configuration data successfully, it releases the CONF_DONE pin, which is pulled high by
a pull-up resistor. A low-to-high transition on CONF_DONE indicates configuration is
complete and initialization of the device can begin.
To ensure DCLK and DATA0 are not left floating at the end of configuration, they must be
driven either high or low, whichever is convenient on your board. Use the dedicated
DATA[0] pin for both PS and AS configuration modes. It is not available as a user I/O
pin after configuration.
For FPP and PS configuration schemes, the configuration clock (DCLK) speed must be
below the specified frequency to ensure correct configuration. No maximum DCLK
period exists, which means you can pause the configuration by halting DCLK for an
indefinite amount of time.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration