EP2AGX95EF29C6N Datasheet, PDF (247/380 Pages) Altera Corporation – Device Interfaces and Integration

July 2012
AIIGX51008-4.3
AIIGX51008-4.3
8. High-Speed Differential I/O Interfaces
and DPA in Arria II Devices
This chapter describes the high-speed differential I/O features and resources, the
functionality of the serializer/deserializer (SERDES), and the dynamic phase
alignment (DPA) circuitry in Arria^® II devices.
This chapter contains the following sections:
■ “LVDS Channels” on page 8–2
■ “LVDS SERDES and DPA Block Diagram” on page 8–7
■ “Differential Transmitter” on page 8–8
■ “Differential Receiver” on page 8–11
■ “Programmable Pre-Emphasis and Programmable V_OD.” on page 8–10
■ “Differential I/O Termination” on page 8–20
■ “PLLs” on page 8–21
■ “LVDS and DPA Clock Networks” on page 8–21
■ “Source-Synchronous Timing Budget” on page 8–23
■ “Differential Pin Placement Guidelines” on page 8–27
■ “Setting Up an LVDS Transmitter or Receiver Channel” on page 8–36
Arria II devices have the following dedicated circuitry for high-speed differential I/O
support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment block (bit slip)
■ DPA block
■ Synchronizer (FIFO buffer)
Arria II devices support the following high-speed differential I/O standards:
■ LVDS
■ mini-LVDS
■ RSDS
■ LVPECL
■ Bus LVDS (BLVDS) for Arria II GX devices
1 True mini-LVDS and RSDS inputs are not supported. The LVPECL I/O standard is
only used for phase-locked loop (PLL) clock inputs in differential mode.
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012
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