EP2AGX95EF29C6N Datasheet, PDF (276/380 Pages) Altera Corporation – Device Interfaces and Integration

8–30
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
If the upper center PLL drives DPA-enabled channels in the lower I/O bank, the
lower center PLL cannot drive DPA-enabled channels in the upper I/O bank, and vice
versa. In other words, the center PLLs cannot drive cross-banks simultaneously, as
shown in Figure 8–25.
Figure 8–25. Invalid Placement of DPA-Disabled Differential I/Os Driven by Both Center PLLs
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center PLL
Center PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation