EP2AGX95EF29C6N Datasheet, PDF (111/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
5–3
Clock Networks in Arria II Devices
Global Clock Networks
Arria II devices provide up to 16 GCLKs that can drive throughout the device, serving
as low-skew clock sources for functional blocks such as adaptive logic modules
(ALMs), digital signal processing (DSP) blocks, embedded memory blocks, and PLLs.
Arria II I/O elements (IOEs) and internal logic can drive GCLKs to create internally
generated GCLKs and other high fan-out control signals; for example, synchronous or
asynchronous clears and clock enables. Figure 5–1 and Figure 5–2 show CLK pins and
PLLs that can drive GCLK networks in Arria II devices.
Figure 5–1. GCLK Networks in Arria II GX Devices
Top Left PLL
CLK[12..15]
Top Right PLL
PLL_1
PLL_2
GCLK[12..15]
GCLK[0..3] (2)
GCLK[8..11]
PLL_5 (1) _{Center PLLs}
PLL_6 ₍₁₎ CLK[8..11]
GCLK[4..7]
PLL_4
PLL_3
Bottom Left PLL
CLK[4..7]
Bottom Right PLL
Notes to Figure 5–1:
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration