EP2AGX95EF29C6N Datasheet, PDF (159/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–51
Bypassing PLL
Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9
counters) factor of one.
Table 5–20 lists the settings for bypassing the counters in Arria II PLLs.
Table 5–20. PLL Counter Settings for Arria II Devices
PLL Scan Chain Bits [0..8] Settings
LSB
MSB
Description
0 (1), X (2) X X X X X X X 1 (3) PLL counter bypassed
X
X X X X X X X 0 (3) PLL counter not bypassed because bit 8 (MSB) is set to 0
Notes to Table 5–20:
(1) For Arria II GX devices.
(2) For Arria II GZ devices
(3) Counter-bypass bit.
f For more information about how to use the PLL scan chain bit settings, refer to the
Phase Locked-Loops Reconfiguration (ALTPLL_RECONFIG) Megafunction User Guide.
1 To bypass any of the PLL counters, set the bypass bit to 1, causing the values on the
other bits to be ignored. To bypass the VCO post-scale counter (K), set the
corresponding bit to 0.
Dynamic Phase-Shifting
The dynamic phase-shifting feature allows the output phases of individual PLL
outputs to be dynamically adjusted relative to each other and to the reference clock
without having to send serial data through the scan chain of the corresponding PLL.
This feature simplifies the interface and allows you to quickly adjust clock-to-out (t_CO)
delays by changing the output clock phase-shift in real time. This adjustment is
achieved by incrementing or decrementing the VCO phase-tap selection to a given
C counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a
time. The output clocks are active during this phase-reconfiguration process.
Table 5–21 lists the control signals that are used for dynamic phase-shifting.
Table 5–21. Dynamic Phase-Shifting Control Signals for Arria II Devices (Part 1 of 2)
Signal Name
Description
Source
PHASECOUNTERSELECT[3:0]
PHASEUPDOWN
Counter select. Four bits decoded to select
either the M or one of the C counters for phase
adjustment. One address maps to select all
C counters. This signal is registered in the PLL
on the rising edge of scanclk.
Selects dynamic phase shift direction;
1 = UP; 0 = DOWN. Signal is registered in the
PLL on the rising edge of scanclk.
Logic array or
I/O pins
Logic array or
I/O pin
PHASESTEP
Logic high enables dynamic phase shifting.
Logic array or
I/O pin
Destination
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration