EP2AGX95EF29C6N Datasheet, PDF (139/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–31
Figure 5–26. Phase Relationship Between PLL Clocks in No-Compensation Mode for Arria II Devices
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port (1)
External PLL Clock Outputs (1)
Note to Figure 5–26:
(1) The PLL clock outputs can lag the PLL input clocks depending on routine delays.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin. The external
clock output pin has a phase delay relative to the clock input pin if connected in this
mode. The Quartus II software TimeQuest Timing Analyzer reports any phase
difference between the two. In normal mode, the delay introduced by the GCLK or
RCLK network is fully compensated. Figure 5–27 shows an example waveform of the
phase relationship of the PLL clocks in normal mode.
Figure 5–27. Phase Relationship Between PLL Clocks in Normal Mode for Arria II Devices
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL Clock Outputs (1)
Note to Figure 5–27:
(1) The external clock output can lead or lag the PLL internal clock signals.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration