EP2AGX95EF29C6N Datasheet, PDF (98/380 Pages) Altera Corporation – Device Interfaces and Integration

4–22
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
18 × 18 Complex Multiplier
You can configure the DSP block to implement complex multipliers with the
two-multiplier adder mode. A single half-DSP block can implement one 18-bit
complex multiplier.
Equation 4–4 shows how you can write a complex multiplication.
Equation 4–4. Complex Multiplication Equation
(a + jb) × (c + jd) = [(a × c) – (b × d)] + j[(a × d) + (b × c)]
To implement this complex multiplication in the DSP block, the real part
[(a × c) – (b × d)] is implemented with two multipliers feeding one subtractor block,
and the imaginary part [(a × d) + (b × c)] is implemented with another two multipliers
feeding an adder block. This mode automatically assumes all inputs are using signed
numbers.
Figure 4–15 shows an 18-bit complex multiplication. This mode automatically
assumes all inputs are using signed numbers.
Figure 4–15. Complex Multiplier Using Two-Multiplier Adder Mode
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
A
C
-
36 _{(A × C) - (B × D)}
(Real Part)
B
D
+
36 _{(A × D) + (B × C)}
(Imaginary Part)
Half-DSP Block
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation