EP2AGX95EF29C6N Datasheet, PDF (295/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
9–9
Configuration Schemes
User Mode
An optional INIT_DONE pin is available, which signals the end of initialization and the
start of user-mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-k pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE pin goes low. When
initialization is complete, the INIT_DONE pin is released and pulled high. When
initialization is complete, the device enters user mode. In user-mode, the user I/O
pins no longer have weak pull-up resistors and function as assigned in your design.
Configuration Schemes
The following sections describe configuration schemes for Arria II devices.
MSEL Pin Settings
Select the configuration scheme by driving the Arria II device MSEL pins either high or
low, as listed in Table 9–6 and Table 9–7. The MSEL input buffers are powered by the
V_CCPD and V_CCPGM power supplies for Arria II GX and GZ devices, respectively.
Altera recommends hardwiring the MSEL[] pins to V_CCPD/V_CCPGM or GND. The
MSEL[3..0] pins have 5-k internal pull-down resistors that are always active.
During POR and during reconfiguration, the MSEL pins must be at LVTTL V_IL and V_IH
levels to be considered logic low and logic high, respectively.
1 To avoid problems with detecting an incorrect configuration scheme, hardwire the
MSEL[] pins to V_CCPD/V_CCPGM or GND without pull-up or pull-down resistors. Do not
drive the MSEL[] pins by a microprocessor or another device.
1 For Figure 9–1 on page 9–12 through Figure 9–30 on page 9–66, MSEL[n..0] represents
MSEL[3..0] for Arria II GX devices and MSEL[2..0] for Arria II GZ devices as listed in
Table 9–6 and Table 9–7, respectively.
Table 9–6. Configuration Schemes for Arria II GX Devices (Part 1 of 2)
Configuration Scheme
FPP
FPP with design security feature,
decompression, or both enabled (2)
PS
MSEL3 MSEL2 MSEL1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
1
1
0
1
MSEL0
0
1
1
0
0
1
0
1
Configuration
POR Delay
Voltage
Standard (V) (1)
Fast
3.3, 3.0, 2.5
Fast
1.8
Fast
3.3, 3.0, 2.5
Fast
1.8
Fast
3.3, 3.0, 2.5
Fast
1.8
Standard
Standard
3.3, 3.0, 2.5
1.8
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration