EP2AGX95EF29C6N Datasheet, PDF (156/380 Pages) Altera Corporation – Device Interfaces and Integration

5–48
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Table 5–16 lists the number of bits for each component of a Arria II GZ PLL.
Table 5–16 also lists the scan chain order of PLL components for the top and bottom
PLLs, which have 10 post-scale counters. The order of bits is the same for the left and
right PLLs, but the reconfiguration bits start with the C6 post-scale counter.
Table 5–16. Top and Bottom PLL Reprogramming Bits for Arria II GZ Devices
Block Name
Number of Bits
Counter
Other (1)
Total
C9 (2)
16
2
18
C8
16
2
18
C7
16
2
18
C6 (3)
16
2
18
C5
16
2
18
C4
16
2
18
C3
16
2
18
C2
16
2
18
C1
16
2
18
C0
16
2
18
M
16
2
18
N
16
2
18
Charge Pump Current
0
3
3
VCO Post-Scale divider (K)
1
0
1
Loop Filter Capacitor (4)
0
2
2
Loop Filter Resistor
0
5
5
Unused CP/LF
0
7
7
Total number of bits
—
—
234
Notes to Table 5–16:
(1) Includes two control bits, rbypass for bypassing the counter, and rselodd to select the output clock duty cycle.
(2) The LSB for the C9 low-count value is the first bit shifted into the scan chain for the top and bottom PLLs.
(3) The LSB for the C6 low-count value is the first bit shifted into the scan chain for the left and right PLLs.
(4) The MSB for the loop filter is the last bit shifted into the scan chain.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation