EP2AGX95EF29C6N Datasheet, PDF (71/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
3–23
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode that has one port
reading from and the other port writing to the same address location with the same
clock. In this mode, you can choose “old data”, “new data” or “don’t care” values as
the output.
For old data mode, a read-during-write operation to different ports causes the RAM
outputs to reflect the “old data” value at that address location.
For new data mode, a read-during-write operation to different ports causes the MLAB
registered output to reflect the “new data” value on the next rising edge after the data
is written to the MLAB memory.
For don’t care mode, the same operation results in a “don’t care” or “unknown” value
on the RAM outputs.
1 Read-during-write behavior is controlled using the RAM MegaWizard Plug-In
Manager. For more information about how to implement the desired behavior, refer to
the Internal Memory (RAM and ROM) Megafunction User Guide.
Figure 3–23 shows a sample functional waveform of mixed-port read-during-write
behavior for old data mode in MLABs.
Figure 3–23. MLABs Mixed-Port Read-During-Write: Old Data Mode
clk_a
wraddress
rdaddress
data_in
wrena
byteena_a
q_b(registered)
A0
A0
AAAA BBBB
CCCC DDDD
A1
A1
EEEE
FFFF
11
01
10
A0 (old data) ^AAAA
11
01
10
AABB A1(old data) DDDD
DDEE
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration