EP2AGX95EF29C6N Datasheet, PDF (130/380 Pages) Altera Corporation – Device Interfaces and Integration

5–22
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Table 5–13 lists the PLL features in Arria II devices.
Table 5–13. PLL Features in Arria II Devices
Feature
Arria II GX PLLs
Arria II GZ PLLs
Top/Bottom PLLs
Left/Right PLLs
C (output) counters
7
10
7
M, N, C counter sizes
1 to 512
1 to 512
1 to 512
Dedicated clock outputs
1 single-ended or 1 differential
pair
3 single-ended or 3 differential
pairs (1), (2)
6 single-ended or
4 single-ended and
1 differential pair
2 single-ended or 1 differential
pair
Clock input pins
4 single-ended or 2 differential
pin pairs
4 single-ended or 2
differential pin pairs
4 single-ended or 2 differential
pin pairs
External feedback input pin
No
Single-ended or differential
Single-ended only
Spread-spectrum input clock
tracking
Yes (3)
Yes (3)
Yes (3)
PLL cascading
Through GCLK and RCLK and
dedicated path between
adjacent PLLs. Cascading
between the general-purpose
PLL and transceiver PLL is
supported in PLL_1 and
PLL_4.
Through GCLK and RCLK
and a dedicated path
between adjacent PLLs
Through GCLK and RCLK and
dedicated path between
adjacent PLLs (4)
Compensation modes
All except external feedback
mode when you use
differential I/Os
All except LVDS clock
network compensation
All except external feedback
mode when you use
differential I/Os
PLL drives DIFFCLK and
Yes
No
Yes
LOADEN
VCO output drives DPA clock
Yes
No
Yes
Phase shift resolution
Down to 96.125 ps (5)
Down to 96.125 ps (5)
Down to 96.125 ps (5)
Programmable duty cycle
Yes
Yes
Yes
Output counter cascading
Yes
Yes
Yes
Input clock switchover
Yes
Yes
Yes
Notes to Table 5–13:
(1) PLL_5 and PLL_6 do not have dedicated clock outputs.
(2) The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in PLL_1 and PLL_3 of EP2AGX95,
EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(3) This is applicable only if the input clock jitter is within the input jitter tolerance specifications.
(4) The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(5) The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Arria II device
can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and C counter
value.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation