EP2AGX95EF29C6N Datasheet, PDF (109/380 Pages) Altera Corporation – Device Interfaces and Integration

July 2012
AIIGX51005-4.2
AIIGX51005-4.2
5. Clock Networks and PLLs in Arria II
Devices
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
which have advanced features in Arria^® II devices that provide dedicated global clock
networks (GCLKs), regional clock networks (RCLKs), and periphery clock networks
(PCLKs). This chapter also includes details reconfiguring the PLL counter clock
frequency and phase shift in real time, allowing you to sweep PLL output frequencies
and dynamically adjust the output clock phase shift.
This chapter contains the following sections:
■ “Clock Networks in Arria II Devices” on page 5–1
■ “PLLs in Arria II Devices” on page 5–22
Clock Networks in Arria II Devices
The GCLKs, RCLKs, and PCLKs available in Arria II devices are organized into
hierarchical clock structures that provide up to 192 unique clock domains
(16 GCLK + 88 RCLK + 88 PCLK) and allow up to 60 unique GCLK, RCLK, and PCLK
clock sources (16 GCLK + 22 RCLK + 22 PCLK) per device quadrant.
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012
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