EP2AGX95EF29C6N Datasheet, PDF (239/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
Arria II External Memory Interface Features
7–37
Arria II GZ Dynamic On-Chip Termination Control
Figure 7–24 shows the dynamic OCT control block. The block includes all the registers
required to dynamically turn on the on-chip parallel termination (R_T OCT) during a
read and turn R_T OCT off during a write.
f For more information about the dynamic OCT control block, refer to the I/O Features
in Arria II Devices chapter.
Figure 7–24. Dynamic OCT Control Block for Arria II GZ Devices
OCT Control
2 ^DFF
OCT Enable
DFF
OCT
Half-Rate Clock
OCT Control Path
HDR
Block
Resynchronization
Registers
Write Clock (1)
Note to Figure 7–24:
(1) The write clock comes from the PLL.
I/O Element Registers
IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. For Arria II GX devices, both top,
bottom, and right IOEs have the same capability. Right IOEs have extra features to
support LVDS data transfer. For Arria II GZ devices, both top and bottom, and left
and right IOEs have the same capability. Left and right IOEs have extra features to
support LVDS data transfer.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration