EP2AGX95EF29C6N Datasheet, PDF (250/380 Pages) Altera Corporation – Device Interfaces and Integration

8–4
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Locations of the I/O Banks
Figure 8–2 shows a high-level chip overview of the Arria II GZ devices.
Figure 8–2. High-Speed Differential I/Os with DPA Block Locations in Arria II GZ Devices
General Purpose
I/O and Memory
Interface
PLL PLL
General Purpose
I/O and Memory
Interface
PLL (1)
PLL (2)
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL (1)
PLL (2)
General Purpose
I/O and Memory
Interface
PLL PLL
General Purpose
I/O and Memory
Interface
Notes to Figure 8–2:
(1) Not available for F780 device package.
(2) Not available for F780 and F1152 device packages.
(3) The PCIe hard IP block is located on the left side of the device only (IOBANK_QL).
Table 8–1 to Table 8–4 list the maximum number of row and column LVDS I/Os
supported in Arria II devices. You can design the LVDS I/Os as true LVDS input,
output buffers, or emulated LVDS output buffers, if the combination does not exceed
the maximum count. For example, there are a total of 56 LVDS pairs of I/Os in 780-pin
EP2AGX45 device row (refer to Table 8–1). You can design up to a maximum of either:
■ 28 true LVDS input buffers with R_D OCT and 28 true LVDS output buffers
■ 56 LVDS input buffers of which 28 are true LVDS input buffers with R_D OCT and
28 requires external 100-termination
■ 28 true LVDS output buffers and 28 emulated LVDS output buffers
■ 56 emulated LVDS output buffers
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation