EP2AGX95EF29C6N Datasheet, PDF (273/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Pin Placement Guidelines
8–27
Differential Pin Placement Guidelines
To ensure proper high-speed operation, differential pin placement guidelines are
established. The Quartus II Compiler automatically checks that these guidelines are
followed and issues an error message if they are not adhered to.
1 DPA-enabled differential channels refer to DPA mode or soft CDR mode;
DPA-disabled channels refer to non-DPA mode.
DPA-Enabled Channels and Single-Ended I/Os
When single-ended I/Os and LVDS I/Os share the same I/O bank, the placement of
single-ended I/O pins with respect to LVDS I/O pins is restricted. The constraints on
single-ended I/Os placement with respect to DPA-enabled or DPA-disabled LVDS
I/Os are the same.
■ Single-ended I/Os are allowed in the same I/O bank, if the single-ended I/O
standard uses the same V_CCIO as the DPA-enabled differential I/O bank.
■ Single-ended inputs can be in the same logic array block (LAB) row as a
differential channel using the SERDES circuitry.
■ Double data rate I/O (DDIO) can be placed within the same LAB row as a SERDES
differential channel but half rate DDIO or single data rate (SDR) output pins
cannot be placed within the same LAB row as a receiver SERDES differential
channel. The input register must be implemented within the FPGA fabric logic.
Guidelines for DPA-Enabled Differential Channels
When you use DPA-enabled channels, you must adhere to the guidelines listed in the
following sections.
DPA-Enabled Channel Driving Distance
If the number of DPA-enabled channels driven by each center or corner PLL exceeds
25 LAB rows, Altera recommends implementing data realignment (bit slip) circuitry
for all the DPA channels.
Using Center and Corner Left and Right PLLs in Arria II GX Devices
If the DPA-enabled channels in a bank are being driven by two PLLs, where the corner
PLL is driving one group and the center PLL is driving another group, there must be
at least one row of separation between the two groups of DPA-enabled channels, as
shown in Figure 8–23. This separation prevents noise mixing because the two groups
can operate at independent frequencies.
No separation is necessary if a single PLL is driving both the DPA-enabled channels
and DPA-disabled channels.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration