EP2AGX95EF29C6N Datasheet, PDF (154/380 Pages) Altera Corporation – Device Interfaces and Integration

5–46
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
1 When you reconfigure the counter clock frequency, you cannot reconfigure the
corresponding counter phase shift settings with the same interface. Instead,
reconfigure the phase shifts in real time with the dynamic phase shift reconfiguration
interface. If you reconfigure the counter frequency, but want to keep the same
non-zero phase shift setting (for example, 90°) on the clock output, you must
reconfigure the phase shift immediately after reconfiguring the counter clock
frequency.
Post-Scale Counters (C0 to C9)
You can configure the multiply or divide values and duty cycle of post-scale counters
in real time. Each counter has an 8-bit high-time setting and an 8-bit low-time setting.
The duty cycle is the ratio of output high- or low-time to the total cycle time, which is
the sum of the two. Additionally, these counters have two control bits, rbypass for
bypassing the counter and rselodd to select the output clock duty cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by 1.
When this bit is set to 0, the high- and low-time counters are added to compute the
effective division of the VCO output frequency. For example, if the post-scale divide
factor is 10, the high- and low-count values could be set to 5 and 5, respectively, to
achieve a 50-50% duty cycle. The PLL implements this duty cycle by transitioning the
output clock from high to low on the rising edge of the VCO output clock. However, a
4 and 6 setting for the high- and low-count values, respectively, would produce an
output clock with a 40-60% duty cycle.
The rselodd bit indicates an odd divide factor for the VCO output frequency along
with a 50% duty cycle. For example, if the post-scale divide factor is 3, the high- and
low-time count values could be set to 2 and 1, respectively, to achieve this division.
This implies a 67%-33% duty cycle. If you require a 50%-50% duty cycle, you can set
the rselodd control bit to 1 to achieve this duty cycle despite an odd division factor.
The PLL implements this duty cycle by transitioning the output clock from high to
low on a falling edge of the VCO output clock. When you set rselodd = 1, you
subtract 0.5 cycles from the high time and you add 0.5 cycles to the low time. For
example:
■ High-time count = 2 cycles
■ Low-time count = 1 cycle
■ rselodd = 1 effectively equals:
■ High-time count = 1.5 cycles
■ Low-time count = 1.5 cycles
■ Duty cycle = (1.5/3) % high-time count and (1.5/3)% low-time count
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation