EP2AGX95EF29C6N Datasheet, PDF (358/380 Pages) Altera Corporation – Device Interfaces and Integration

10–2
Chapter 10: SEU Mitigation in Arria II Devices
Configuration Error Detection
Configuration Error Detection
In configuration mode, a frame-based CRC is stored in the configuration data and
contains the CRC value for each data frame.
During configuration, the Arria II device calculates the CRC value based on the frame
of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until either the device detects an error or
configuration is complete.
In Arria II devices, the CRC value is calculated during the configuration stage. A
parallel CRC engine generates 16 CRC check bits per frame and then stores them into
the configuration RAM. The configuration RAM chain used for storing CRC check
bits is 16 bits wide and its length is equal to the number of frames in the device.
User Mode Error Detection
Arria II devices have built-in error detection circuitry to detect data corruption by soft
errors in the configuration RAM cells. This feature allows all configuration RAM
contents to be read and verified to match a configuration-computed CRC value. Soft
errors are changes in a configuration RAM’s bit state due to an ionizing particle.
The error detection capability continuously calculates the CRC of the configured
configuration RAM bits and compares it with the pre-calculated CRC. If the CRCs
match, there is no error in the current configuration RAM bits. The process of error
detection continues until the device is reset by setting nCONFIG low.
To enable the error detection process when the device transitions into user mode, turn
on the Enable Error Detection CRC option on the Error Detection CRC page of the
Device and Pin Options dialog box in the Quartus II software.
A single 16-bit error detection CRC calculation is done on a per-frame basis. After the
error detection circuitry has finished the CRC calculation for a frame, the resulting
16-bit signature is hex 0000. If the error detection circuitry detects no configuration
RAM bit errors in a frame, the output signal CRC_ERROR is 0. If the circuitry detects a
configuration RAM bit error in a frame in the device, the resulting signature is
non-zero and the error detection circuitry starts searching for the error bit location.
The error detection circuitry in Arria II devices calculates CRC check bits for each
frame and pulls the CRC_ERROR pin high when it detects bit errors in the chip. Within a
frame, it can detect all single-bit, double-bit, and triple-bit errors. The probability of
more than three configuration RAM bits being flipped by a single event upset (SEU) is
very low. In general, the probability of detection for all error patterns is 99.998%.
The error detection circuitry reports the bit location and determines the type of error
for all single-bit errors and over 99.641% of double-adjacent errors. The probability of
other error patterns is very low and the reporting of bit location is not guaranteed.
You can also read the error bit location through the JTAG and the core interface.
Before the error detection circuitry detects the next error in another frame, you must
shift erroneous bits out from the error message register (EMR) with either the JTAG
instruction, SHIFT_EDERROR_REG, or the core interface. The CRC circuitry continues to
run, and if an error is detected, you must decide whether to complete the
reconfiguration or to ignore the CRC error.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
February 2014 Altera Corporation