EP2AGX95EF29C6N Datasheet, PDF (178/380 Pages) Altera Corporation – Device Interfaces and Integration

6–14
Chapter 6: I/O Features in Arria II Devices
I/O Structure
High-Speed Differential I/O with DPA Support
Arria II devices have the following dedicated circuitry for high-speed differential I/O
support:
■ Differential I/O buffer
■ Transmitter serializer
■ Receiver deserializer
■ Data realignment circuitry
■ Dynamic phase aligner (DPA)
■ Synchronizer (FIFO buffer)
■ Phase-locked loops (PLLs)
f For more information about DPA support, refer to the High-Speed Differential I/O
Interfaces and DPA in Arria II Devices chapter.
Programmable Current Strength
The output buffer for each Arria II I/O pin has a programmable current-strength
control for certain I/O standards. You can use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control. Table 6–7 and Table 6–8 list the
programmable current strength settings for Arria II devices.
Table 6–7. Programmable Current Strength for Arria II GX Devices (Note 1) (Part 1 of 2)
I/O Standard
3.3-V LVTTL (2)
3.3-V LVCMOS (2)
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
I_OL / I_OH Current Strength Setting (mA)
for Top, Bottom, and Right I/O Pins
[12], 8, 4
[2]
16, 12, 8, 4
16, 12, 8, 4
16, 12, 8, 4
16, 12, 10, 8, 6, 4, 2
16, 12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
12, 8
16
12, 10, 8
16, 12
12, 10, 8
12, 10, 8
16
12, 10, 8
16
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation